In BiCMOS technology processes, both bipolar and CMOS devices are formed on the same substrate or chip. In certain applications, it is desirable to form an MOS EEPROM memory cell on the same substrate as other bipolar circuits. A single poly EEPROM memory cell uses a coupling capacitor to supply a voltage to an oxide tunnel diode window, and traditionally, a shallow implant or buried layer (BN+) is used to dope active regions under the tunnel diode window region and the coupling capacitor region. The highly n-doped regions are electrically isolated from other proximate transistors for proper functioning of the EEPROM by forming a shallow trench isolation (STI) field.
Process steps to develop sinker implants in a bipolar or BiCMOS processes typically drive the sinker implant or dopant below the depth of an STI. U.S. Pat. No. 5,248,624 to Icel et al. entitled “Method Of Making Isolated Vertical PNP Transistor in a Complementary BiCMOS Process with EEPROM Memory” uses a sinker in the formation of bipolar transistors, but only for improving the isolation of a vertical PNP transistor. U.S. Pat. No. 6,438,030 to Hu et al. entitled “Non-volatile Memory, Method of Manufacture, and Method of Programming” describes the formation of shallow trench isolation structures and p-well implants to isolate transistor devices, however, no sinker implants are used.
Accordingly, what is needed is an improved process and structure integrating an MOS EEPROM memory cell into a BiCMOS process without adding additional masks or process steps and potentially integrating bipolar process steps with MOS process steps.